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A 7T Security Oriented SRAM Bitcell
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DOI：10.1109/tcsii.2018.2886175.png)
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摘要
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Power analysis (PA) attacks have become a serious threat to security systems by enabling secret data extraction through the analysis of the current consumed by the power supply of the system. Embedded memories, often implemented with six-transistor static random access memory (SRAM) cells, serve as a key component in many of these systems. However, conventional SRAM cells are prone to side-channel PA attacks due to the correlation between their current characteristics and written data. To provide resiliency to these types of attacks, we propose a security-oriented 7T SRAM cell, which incorporates an additional transistor to the original 6T SRAM implementation and a two-phase write operation, which significantly reduces the correlation between the stored data and the power consumption during write operations. The proposed 7T SRAM cell was implemented in a 28 nm technology and demonstrates over 1000x lower write energy standard deviation between write 1 and 0 operations compared to a conventional 6T SRAM. In addition, the proposed cell has a 39%-53% write energy reduction and a 19%-38% reduced write delay compared to other PA resistant SRAM cells.
Keyword:
Static random access memory (SRAM)
side-channel attacks (SCA)
differential power analysis (DPA)
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