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A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate
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DOI：10.1109/TCSI.2019.2941703.png)
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Video processing requires an increasing amount of buffered data. The paper proposes a multi-line buffer circuit that stores compressed data thus saving logic and power. The lossy compression algorithm provides the output stream with a fixed, decided by the user, delay from the input stream. Further, the amount of memory of the compressed buffer can be designed to trade off the correctness of the output with the logic resources footprint. The circuit is tested in a computer vision processing chain as a binary line buffer for the stream of foreground pixels. The paper also proposes a multi-line buffer circuit that integrates a morphological operation. The latter, when compared against the state of the art and against the proposed multi-line lossy buffer, allows larger saving of logic resources (up to 75) and power (up to 85), with reduced penalty on video quality.
Keyword:
Streaming media
Memory management
Buffer storage
Image coding
Transform coding
Shift registers
Low power design
VLSI
sequential circuits
shift register
data compaction and compression
computer vision
video compression
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