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A Block PatchMatch-Based Energy-Resource Efficient Stereo Matching Processor on FPGA

delete2022-07-01
delete6
PRE
AI
H
Hongyu Wang
W
Wei Zhou
X
Xiangyu Zhang
X
Xin Lou *
DOI:10.1109/TCSI.2022.3161266delete
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摘要

摘要

En 中文
This paper presents a field programmable gate array (FPGA)-based, high-performance and energy-resource efficient stereo matching processor. The proposed processor executes block-level PatchMatch-based stereo matching algorithm with a random search strategy to avoid estimation of all disparity levels. To take advantages of different block scales, a coarse-to-fine multi-scale propagation (MSP) scheme is proposed for label update. Based on that, a dedicated hardware architecture is further proposed to explore the benefit of the algorithm. Experimental results show that the proposed FPGA-based processor, running at 350MHz, achieves a peak performance of 1920x1080.165.7 frame per second (FPS) at 128 disparity levels with 3.35W power dissipation. The energy and resource efficiency of the proposed design outperforms state-of-the-art FPGA-based stereo matching processors. When disparity level increases to 256, the computing resource increment of the proposed design is much less than existing designs because random search instead of winner-takes-all (WTA) is utilized. Moreover, unlike existing dedicated stereo matching processors which output only disparity information, the proposed design is also capable of deriving plane slant. This information can be beneficial for follow-up tasks like 3D reconstruction.
Keyword:
Costs
Hardware
Real-time systems
Computational complexity
Three-dimensional displays
Field programmable gate arrays
Cameras
Stereo matching
PatchMatch
multi-scale propagation (MSP)
energy-resource efficient
field programmable gate array (FPGA)

期刊

IEEE Transactions on Circuits and Systems I-Regular Papers 封面图
IEEE Transactions on Circuits and Systems I-Regular Papers
IF:
5.2
论文数:
9.9K
被引数:
2.2W

机构

S
ShanghaiTech University
学者数:
9.7K
论文数: 5.9K
被引数: 1.6W
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