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A Charge-Redistribution Phase-Domain ADC Using an IQ-Assisted Binary-Search Algorithm
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DOI：10.1109/TCSI.2017.2681461.png)
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Phase-domain Analog-to-Digital Converters (Ph-ADCs) have been considered for power-efficient implementation of body-area network transceivers employing phase demodulation. Conventional implementations of the Ph-ADCs, which work based on a full-flash zero-crossing algorithm, use linear resistive/current combiners to determine the thermometer digital code of the signal phase. These architectures suffer from high-accuracy requirements, high-circuit complexity, and highpower consumption. Therefore, in this paper, a new IQ-assisted binary-search algorithm is proposed for implementing the Ph-ADC. The proposed Ph-ADC architecture avoids employing the power-hungry linear combiner. Moreover, for an N-bit Ph-ADC, the proposed algorithm requires only N+1 comparisons, whereas the conventional full-flash counterpart demands 2N-1 comparisons. Based on the proposed architecture, two different 5-bit charge-redistribution Ph-ADCs are designed and one of them is fabricated in a standard 0.18-mu m CMOS technology. The prototype achieves an ENOB of 4.85 bits at 1 MS/s, while dissipating 12.9 mu W from a 1.2-V supply.
Keyword:
Phase-domain analog-to-digital converter
IQ-assisted binary search
charge-redistribution Ph-ADC
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