.png){kind=icon}
返回
A chip-multiprocessor architecture with speculative multithreading
.png){kind=icon}
PRE
AI
DOI：10.1109/12.795218.png)
.png){kind=icon}
原文求助.png){kind=icon}
分享.png){kind=icon}
收藏
摘要
En 中文
Much emphasis is now placed on chip-multiprocessor (CMP) architectures for exploiting thread-level parallelism in an application. In such architectures, speculation may be employed to execute applications that cannot be parallelized statically. In this paper, we present an efficient CMP architecture for speculative execution of sequential binaries without source recompilation. We present the software support that enables identification of threads from a sequential binary. The hardware includes a memory disambiguation mechanism that enables the detection of interthread memory dependence violations during speculative execution. This hardware is different from past proposals in that it does not rely on a snoopy-based cache-coherence protocol. Instead, it uses an approach similar to a directory-based scheme. Furthermore, the architecture includes a simple and efficient hardware mechanism to enable register-level communication between on-chip processors. Evaluation of this software-hardware approach shows that it is quite effective in achieving high performance when running sequential binaries.
Keyword:
chip-multiprocessor
speculative multithreading
data-dependence speculation
control speculation
期刊
IF:
3.8
论文数:
5.3K
被引数:
9.8K
机构
暂无机构信息
引用论文
Antigen Identification for Orphan T Cell Receptors Expressed on Tumor-Infiltrating Lymphocytes肿瘤浸润淋巴细胞上表达的孤儿T细胞受体的抗原鉴定.png)
Cell
OAAI
CellIF0
OAAI分享收藏分享收藏分享收藏分享收藏
查看更多内容