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A CMOS image sensor with 14-Bit column-parallel 3rd order incremental sigma-delta converters
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DOI：10.1016/j.sna.2020.112162.png)
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Abstract
En 中文
This paper presents the characterization results and the experimental evaluation of a test chip imager development, employing column-parallel oversampling converters as a means to mitigate both thermal and flicker noise contributions, by using specifically noise-shaping single-bit incremental converters to provide low output noise digital samples in a short period of time. The main goal of this paper is present the fabricated imager based on the designed signal converter type and to use such types of converters in a future test chip development that ultimately can reach sub-electron system readout noise performance. Lastly, this research paper shows the measured performance of the developed 14 bit incremental converter-based imager with 1% system non-linearity, 700mV+ ADC input range and 2.67eand 3.85etotal readout chain input-referred electrical and input-referred optical readout noise, respectively. The sensor was fabricated with a Tower Jazz 180nm Image Sensor Process Development Kit, namely the TS18IS 4M1L module, allowing for 1.8V/3.3V devices, 4 metal layers and Well-buried devices - the Triple Well process. (C) 2020 Elsevier B.V. All rights reserved.
Keywords:
Noise shaping
Digital CDS
ISD
Quantization noise
INL
DNL
CMOS
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