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A CMOS voltage reference with low temperature coefficient
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DOI：10.1016/j.aeue.2024.155649.png)
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This article introduces a CMOS voltage reference with low temperature coefficient (TC), high power supply rejection ratio (PSRR). Anew self-biasing loop is proposed to generate a zero temperature characteristic current for the stacked diode-connected MOS transistors (SDMTs) to improve TC performance of reference voltage. Moreover, the drain induced barrier lowering (DIBL) effect compensation at the output stage absorbs power- related currents, improving linear sensitivity (LS). It employs voltage self-regulating technique to reduce the impact of power supply ripple on the output. The majority of MOSFETs operate in the sub-threshold region to minimize power consumption. Designed and simulated in a 65 nm CMOS process, the voltage reference output 418 mV with an average TC of 14.05 ppm/degrees C across a-40 degrees C to 125 degrees C temperature range. The proposed voltage reference LS is about 0.012 mV/V in the 0.85- 1.32 V range. Significantly, the PSRR achieves-101 dB at 1 Hz and-62 dB at 1 MHz.
Keyword:
Voltage reference
Self-biasing loop
Low temperature coefficient
Voltage self-regulating
DIBL effect compensation
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3.2
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5.8K
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