A comparative analysis of cache designs for vector processing

doi:10.1109/12.754999

A comparative analysis of cache designs for vector processing

1999-03-01

2

PRE

AI

孙铜 (Tong Sun) *

Q

Qing Yang

DOI：10.1109/12.754999

原文链接

原文求助

摘要

En 中文

This paper presents an experimental study on cache memory designs for vector computers. We use an execution-driven simulator to evaluate vector cache performance of a set of application programs from Perfect Club and SPEC92 benchmark suites. Our simulation results uncover a few important facts which were unknown before: First of all, the prime-mapped cache that we newly proposed shows great performance potential in vector processing environment. Because of its conflict-free property, the prime-mapped cache performs significantly better than conventional cache designs for all applications considered. Second, performance results on the benchmarks indicate that data locality in vector processing does exist, although the effects of line size, associativity replacement algorithm, and prefetching scheme on cache performance are very different from what has been commonly believed. A medium size vector cache (e.g., 128Kbytes) eliminates the necessity for a large number of interleaved memory banks in vector computers. Our experiments show that the vector computer that has a medium size prime-mapped cache with small cache line size and limited amount of prefetching provides significant speedup over conventional vector computers without cache. Performance results reported in this paper can also provide guidance to general-purpose computer designers to enhance cache performance for numerical applications.

Keyword:

performance evaluation

cache memories

memory hierarchy

vector processing

simulation

benchmarks

A comparative analysis of cache designs for vector processing

摘要

期刊

机构

引用论文