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A Configurable FPGA SIMD architecture for FSM-oriented software testing acceleration
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DOI：10.1007/s10586-026-06433-x.png)
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Abstract
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Software testing is a critical phase in the development lifecycle, directly influencing the reliability and performance of the final product. As software systems grow increasingly complex, traditional testing approaches become progressively time-consuming and resource-intensive. This paper presents a novel framework that accelerates software testing by leveraging configurable Single Instruction, Multiple Data (SIMD) architectures implemented on Field-Programmable Gate Arrays (FPGAs). FPGAs are gaining prominence due to their flexibility, parallelism, and energy efficiency, making them ideal platforms for high-throughput applications. By using extracted Finite State Machine (FSM) models representing software behavior, the proposed framework systematically offloads test execution to a reconfigurable SIMD structure on FPGA, enabling parallel and cycle-accurate validation. A prototype system was developed and evaluated, achieving up to 115 $$\times$$ speedup in slow FPGA mode and an average speedup of 81 $$\times$$ compared to conventional software testing methods. These results highlight the significant potential of FPGA-based acceleration in reducing testing time and improving overall development productivity. The proposed approach offers a scalable, customizable, and efficient solution, paving the way for integrating reconfigurable computing into mainstream software testing workflows.
Keywords:
Configurable SIMD architecture
FPGA acceleration
Parallel processing
Software testing
FSM modeling
Custom hardware design
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