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A Delay Relaxed RLS-DCD Algorithm for Real-Time Implementation
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DOI：10.1109/TCSII.2017.2706367.png)
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The recursive least squares algorithm (RLS) using dichotomous coordinate descent (DCD) iterations, namely, RLS-DCD, is regarded to be well suited for hardware implementation because of its small computational complexity compared to the classical RLS algorithm. While this is true, yet another important aspect that ultimately determines its applicability for real-time applications with high sample rates, is its iteration bound. In this brief, we discuss this issue and propose a modified RLS-DCD algorithm based on delay relaxation whose iteration bound can be reduced arbitrarily. The degradation in convergence speed is shown to be tolerable, which results in still much faster convergence compared to the normalized least mean square algorithm.
Keyword:
Adaptive filter
RLS
DCD
delay relaxation
iteration bound
FPGA
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