A Design Framework for Hardware-Efficient Logarithmic Floating-Point Multipliers

Tingting Zhang

doi:10.1109/TETC.2024.3365650

2024-10-01

PRE

Tingting Zhang

Zijing Niu

韩杰 (Jie Han) *

DOI：10.1109/TETC.2024.3365650

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摘要

En 中文

The symbiotic use of logarithmic approximation in floating-point (FP) multiplication can significantly reduce the hardware complexity of a multiplier. However, it is difficult for a limited number of logarithmic FP multipliers (LFPMs) to fit in a specific error-tolerant application, such as neural networks (NNs) and digital signal processing, due to their unique error characteristics. This article proposes a design framework for generating LFPMs. We consider two FP representation formats with different ranges of mantissas, the IEEE 754 Standard FP Format and the Nearest Power of Two FP Format. For both logarithm and anti-logarithm computation, the applicable regions of inputs are first evenly divided into several intervals, and then approximation methods with negative or positive errors are developed for each sub-region. By using piece-wise functions, different configurations of approximation methods throughout applicable regions are created, leading to LFPMs with various trade-offs between accuracy and hardware cost. The variety of error characteristics of LFPMs is discussed and the generic hardware implementation is illustrated. As case studies, two LFPM designs are presented and evaluated in applications of JPEG compression and NNs. They do not only increase the classification accuracy, but also achieve smaller PDPs compared to the exact FP multiplier, while being more accurate than a recent logarithmic FP design.

Keyword:

Hardware

Standards

Transform coding

Training

Costs

Artificial neural networks

Image coding

Floating-point multiplier

logarithmic multiplier

neural networks

JPEG compression