A Hardware Decoder Architecture for General String Matching Technique

Kailun Zhou

doi:10.1109/JETCAS.2016.2599876

2016-12-01

PRE

Kailun Zhou

Liping Zhao

Tao Lin *

DOI：10.1109/JETCAS.2016.2599876

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摘要

En 中文

This paper proposes a low cost hardware decoder design and architecture that supports general string matching (SM) using both a primary reference buffer (PRB) and a secondary reference buffer (SRB). An SM decoding module mainly performs string copy operation. The SM decoding module can also support intra block copy and palette decoding because both are actually two special cases of general string copy. The proposed architecture has four pipeline stages. The theoretical lowest system clock frequency required to guarantee worst case string copy operation using single-port SRAM is lower than the video output pixel rate, which is the product of frame resolution and frame rate. The design uses four pieces of SRAMs with size of 24K bytes, 16.5K bytes, 4K bytes, and 3K bytes, respectively. The first one is specific to SM and the other three are shared by traditional hybrid decoding operations. The SM decoding module has 69.5K logic gate count and can achieve 60 fps real time SM decoding for 4K (4096 x 2160) video at 218 MHz working frequency.

Keyword:

Hardware decoder

string matching

screen content coding (SCC)

VLSI architecture