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A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders
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AI
DOI：10.1016/j.fss.2011.06.006.png)
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A new hardware-friendly mathematical method for realizing low-complexity universal Adder cells as well as its efficient hardware implementations is proposed in this paper. This method can be used in binary logic, Multiple-Valued Logic (MVL) and specifically digital fuzzy systems. The proposed mathematical method can be implemented in both voltage and current modes. The voltage-mode hardware implementation is very simple and is based on input capacitors and MVL or analog inverters and buffers. In addition, the current-mode hardware implementation leads to simple and efficient structures for digital fuzzy systems. Simulations are carried out for ternary logic as well as for digital fuzzy logic with high precision by using 180 nm standard CMOS technology and at 1.8 V supply voltage. Simulation results demonstrate that the proposed designs have excellent functionality and are very suitable for implementing MVL and fuzzy arithmetic circuits. (C) 2011 Elsevier B.V. All rights reserved.
Keyword:
Full Adder
Digital fuzzy sets
Fuzzy hardware
Multiple-Valued Logic (MVL)
Radix-r
期刊
IF:
2.7
论文数:
7.6K
被引数:
1.5W
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