A high performance hardware accelerator for dynamic texture segmentation

doi:10.1016/j.sysarc.2015.09.005

A high performance hardware accelerator for dynamic texture segmentation

2015-11-01

6

PRE

AI

J

João Pedro Ferraz Mourão Maya Barbosa

A

Antonyus P. A. Ferreira *

R

Rodrigo Camarotti Ferreira da Rocha

Djeefther S. Albuquerque

E

Edna Barros

DOI：10.1016/j.sysarc.2015.09.005

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Hardware accelerators such as general-purpose GPUs and FPGAs have been used as an alternative to conventional CPU architectures in scientific computing applications, and have achieved good speed-up results. Within this context, the present study presents a heterogeneous architecture for high-performance computing based on CPUs and FPGAs, which efficiently explores the maximum parallelism degree for processing video segmentation using the concept of dynamic textures. The video segmentation algorithm includes processing the 3-D FFT, calculating the phase spectrum and the 2-D IFFT operation. The performance of the proposed architecture based on CPU and FPGA is compared with the reference implementation of FFTW in CPU and with the cuFFT library in GPU. The performance report of the prototyped architecture in a single Stratix IV FPGA obtained an overall speedup of 37x over the FFTW software library. (C) 2015 Elsevier ay. All rights reserved.

Keyword:

Video segmentation

FFT

IFFT

FPGA

Hardware architecture

High performance system

A high performance hardware accelerator for dynamic texture segmentation

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