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A Hybrid Analog-to-Digital Conversion Algorithm With Sub-Radix and Multiple Quantization Thresholds
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DOI：10.1109/TCSI.2016.2561758.png)
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摘要
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This paper presents an analog-to-digital (A-to-D) conversion algorithm to break through the speed limitation of the analog-to-digital converters in advanced technology. The proposed A-to-D conversion algorithm utilizes the benefits of the speed-up techniques of sub-radix and multi-bit per cycle. We model the V-in - V-q transfer curves into linear equations with hardware-like parameters for in-depth analysis. The design constraints, guidelines, tradeoffs, and figure of merit (FoM) are provided for architecture optimization.
Keyword:
Analog-to-digital (A-to-D) conversion
multi-bit per cycle
redundancy
sub-radix
time-interleaved
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