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A Low-Error, Memory-Based Fast Binary Logarithmic Converter
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DOI：10.1109/TCSII.2019.2945336.png)
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This brief presents a memory based fast binary logarithmic converter based on a piecewise linear approximation technique. The proposed method is simple and arithmetic operation-less, which achieves 10(-4) to 10(-3) maximum absolute error (MAE) while maintaining a high speed. The approach partitions the logarithmic curve of the fractional component into 2L uniform regions and a block RAM (size 2(L)x bits) stores the approximate value of each sub-region. For any number, most significant L bits of the fractional component address the memory location of the logarithmic converter. The hardware synthesis result, implemented with 26 bits fractional precision on Virtex-6 field-programmable gate array device, shows 75% improvement in MAE and 27% decrease in critical path delay compared to the current state-of-the-art techniques in the worst-case scenario. In Otsu's image thresholding algorithm, the proposed logarithmic converter with 3.08 (= 2(8)x12) kbits memory size adequately meets the accuracy requirement for improved image segmentation.
Keyword:
Hardware
Image segmentation
Interpolation
Circuits and systems
Delays
Memory management
Design methodology
Logarithmic conversion
piecewise linear approximation
image segmentation
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