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A Low Valid Throughput Loss LDPC Codec Architecture With Variable Code Rate
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DOI：10.1109/TCSII.2023.3344221.png)
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Shortening is a rate-compatible technology that can improve LDPC error correction performance by modifying the code rate. However, as the code rate decreases, the throughput of valid data drops rapidly. Reducing the attenuation of valid throughput at low code rates is challenging. For this reason, this brief proposes two contributions. First, a Block Tag-based encoding method is presented with a non-fixed code length, which reduces the latency caused by fixed-length communications. Second, a novel Time Division Multiplexing (TDM) architecture is developed to improve valid throughput, reducing resource utilization compared to conventional multiplexers. Based on the above contributions, the codec is implemented on FPGA and the results show that the valid throughput loss is low in changing from high to low code rates.
Keyword:
LDPC codec
throughput loss
time division multiplexing
non-fixed code length
FPGA
期刊
I
IF:
4.9
论文数:
8.8K
被引数:
2.5W
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