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A Multiplierless Architecture for Image Convolution in Memory
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DOI：10.3390/jlpea15040063.png)
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摘要
En 中文
Image convolution is a commonly required task in machine vision and Convolution Neural Networks (CNNs). Due to the large data movement required, image convolution can benefit greatly from in-memory computing. However, image convolution is very computationally intensive, requiring (n-(k-1))2 Inner Product (IP) computations for convolution of a nxn image with a kxk kernel. For example, for a convolution of a 224 x 224 image with a 3 x 3 kernel, 49,284 IPs need to be computed, where each IP requires nine multiplications and eight additions. This is a major hurdle for in-memory implementation because in-memory adders and multipliers are extremely slow compared to CMOS multipliers. In this work, we revive an old technique called 'Distributed Arithmetic' and judiciously apply it to perform image convolution in memory without area-intensive hard-wired multipliers. Distributed arithmetic performs multiplication using shift-and-add operations, and they are implemented using CMOS circuits in the periphery of ReRAM memory. Compared to Google's TPU, our in-memory architecture requires 56x less energy while incurring 24x more latency for convolution of a 224 x 224 image with a 3 x 3 filter.
Keyword:
distributed arithmetic
inner product
multiply and accumulate (MAC)
shift-add
non-volatile memory
resistive RAM
convolution
期刊
J
IF:
1.8
论文数:
41
被引数:
516
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