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A Neural Network-Enhanced Digital Background Calibration Algorithm for Residue Amplifier Nonlinearity in Pipelined ADCs
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AI
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Z
H
张
D
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T
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X
H
DOI：10.1109/TCSII.2025.3580062.png)
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Abstract
En 中文
This brief proposes a neural network-enhanced digital background calibration scheme for calibrating the linear and the third-order nonlinear gain errors of the residue amplifier (RA) in pipelined ADCs. A customized convolutional neural network (CNN) is designed to extract the information of the linear and the third-order nonlinear gain errors of RA with dither injection. Compared to traditional correlation-based calibration algorithms, the proposed method can significantly improve convergence speed and robustness against dither capacitor mismatch. Compared with previous neural network-based calibration techniques which are commonly used for foreground calibration, the proposed method can operate in background to follow error variations without any risk of signal fidelity problems. Off-chip validation with a silicon-proven 14-bit 1.3 GS/s pipelined ADC shows that, after calibration, the SNDR and SFDR are improved from 46.6 dB and 55.2 dB to 63.1 dB and 80.4 dB, respectively. Moreover, the proposed method takes only 75K samples to reach convergence, whereas traditional algorithms require several to hundreds of millions of samples to achieve convergence (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10{^{{2}}} \sim 10{^{{4}}}$ </tex-math></inline-formula> times faster). The implementation result shows that the power consumption of the proposed calibrator is 34.8 mW at 1.3 GHz clock frequency.
Keywords:
Convolutional neural network
nonlinear gain errors extraction
background calibration
fast convergence
pipelined ADC
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