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A New ECC Configuration Method for DRAM System Considering Metadata
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DOI：10.1109/TC.2024.3521545.png)
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摘要
En 中文
In this paper, a new ECC (error correcting code) solution for DRAM (dynamic random access memory) in computing systems is proposed. Existing papers on ECC for DRAM systems do not consider storage space for metadata. The methodology proposed in this paper considers storing metadata attached to a cacheline data in DRAM. We infer the maximum number of single-chip error correction cases that a linear code can support while considering metadata storage space. This can be said to be the maximum theoretical correction probability for a single chip error. A methodology to construct a code with maximum single-chip error correction is presented. A decoding methodology for the code is proposed. The proposed ECC solution can correct not only single chip failure but also additional small bit errors. We calculate the correction capability of the proposed methodology and verified it through simulation. The encoder and decoder hardware were synthesized and compared with existing methodologies.
Keyword:
Random access memory
Error correction codes
Metadata
Decoding
DRAM chips
Memory management
Error correction
Linear codes
Costs
Clocks
Error correcting code
DRAM system
single device data correction
metadata
