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A Novel Architecture for Elementary-Check-Node Processing in Nonbinary LDPC Decoders
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DOI：10.1109/TCSII.2016.2551550.png)
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摘要
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This brief presents an efficient architecture design for elementary-check-node processing in nonbinary low-density parity-check decoders based on the extended min-sum algorithm. This architecture relies on a simplified version of the bubble check algorithm and is implemented by the means of first-in-first-out. The adoption of this new design at the check node level results in a high-rate low-cost full-pipelined processor. A proof-of-concept implementation of this processor shows that the proposed architecture halves the occupied the field-programmable gate array (FPGA) surface and doubles the maximum frequency without modifying the input/output behavior of the previous one.
Keyword:
Channel coding
communication systems decoding
Field Programmable Gate Array
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