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A Novel Dynamic Detection for Flash Memory
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DOI：10.1109/TCSII.2019.2920723.png)
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摘要
En 中文
The incorporation of powerful soft-decision error correction codes (e.g., LDPC) to replace legacy hard-decision codes (e.g., BCH) can boost the reliability of flash memory beyond its current limits at the expense of additional reading latency to generate soft information, namely in the form of log-likelihood ratios (LLRs). Unfortunately, the memory channel varies significantly depending on several factors (e.g., temperature, parasitic coupling, and retention time) which renders the use of precomputed LLR lookup table (LUT) ineffective especially as the device ages. In fact, the estimated LLRs need to be regularly updated to avoid any performance degradation. We provide a dynamic yet low-latency blind detection algorithm which is able to adaptively adjust the hard/soft-decision boundaries and estimate the corresponding LLR codebook. The proposed demodulator offers near-optimal performance with low-complexity overhead.
Keyword:
Threshold voltage
Estimation
Decoding
Heuristic algorithms
Parity check codes
Reliability
Voltage control
Flash memory
soft detection
LLR estimation and error correction
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