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A Novel Phase-Interleaving Algorithm for Multiterminal Systems
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DOI：10.1109/TPEL.2009.2034006.png)
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摘要
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This paper introduces a novel phase-interleaving algorithm for asymmetric multiterminal power converters. Using a variable phase interleaving (VI), the first harmonic of the dc-link current and voltage can be thoroughly eliminated even under the situation where the input voltage and current of each converter differ. This means that the cost and size of the dc-link capacitor can be significantly reduced compared to when the standard (symmetric) interleaving algorithm is used. The VI-algorithm does not require any additional hardware and has only slight influence on the control loop of the converters when compared to the standard solution, which simplifies the integration of this algorithm. As a concrete application, the VI-algorithm is integrated into a photovoltaic inverter with three independent input converters. This paper also provides a method for determining the required dc-link capacitance through a worst-case analysis. Furthermore, a performance comparison between edge-aligned fixed interleaving, center-aligned fixed interleaving and VI and is given.
Keyword:
Multiterminal
variable interleaving (VI)
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6.5
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1.7W
被引数:
8.3W
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