A power-efficient dynamic-time current mode comparator

doi:10.1016/j.aeue.2023.154934

2023-11-01

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DOI：10.1016/j.aeue.2023.154934

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摘要

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This paper presents a power-efficient dynamic-time current comparator for current mode signal processing. The proposed circuit utilizes a switched feedback-based inverter and a clock-shaping circuit. The switched feedbackbased inverter can detect the polarity of the sensed current from the current subtraction circuit. While the clockshaping circuit can manage the power consumption. Since the proposed current comparator exhibits a high sensitivity to ultra-low input current with a low input offset, it can be exploited in a current mode successiveapproximation-register analog-to-digital converters for a wide range of wearable applications. Moreover, a design methodology for an efficient and robust current comparator is presented. The circuit is designed and simulated in TSMC 0.13 mu m CMOS technology, and occupies a silicon area of 7834 mu m2. The proposed current comparator consumes a power of 14 mu W with a single power supply of 1.2 V. It provides a resolution of 2 nA, and a delay of 4.6 ns. Moreover, the post-layout simulation results indicate a good agreement compared to the prior art.

Keyword:

Dynamic-time comparator

Current mode SAR ADC

Current mode circuits

Low-power

Post-layout simulation