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A Predictive SAR ADC Architecture
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DOI：10.1109/TCSI.2025.3525619.png)
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A SAR architecture is proposed that employs a predictive technique to increase the conversion speed. In this new technique, the comparator operates in parallel with the logic and DAC, reducing the SAR timing budget per cycle to only one comparator decision time plus its clock generation. Moreover, a clock and input signal distribution method is presented that improves clock phase matching in a time-interleaved system. This is accomplished by delivering the primary clock to each channel and generating their interleaved phases locally. Realized in 28-nm CMOS technology, a 6-bit 10-GS/s 17.6-mW prototype achieves an SNDR of 31.2 dB at an input frequency of 4.96 GHz and a figure of merit equal to 59 fJ per conversion step.
Keyword:
Clocks
Delays
Logic
Circuits
Voltage
Topology
Scholarships
Redundancy
Prototypes
Noise
Analog-to-digital converters (ADC)
successive approximation (SAR)
time interleaved
predictive
ring counter
clock distribution
期刊
IF:
5.2
论文数:
9.8K
被引数:
2.2W
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22.4 A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration22.4 一种具有基于扰动背景定时偏斜校准和基于位分布背景乒乓比较器失调校准的4.8GS/s 7-ENoB时间交织SAR ADC
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