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A Probabilistic Prediction-Based Fixed-Width Booth Multiplier for Approximate Computing
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DOI：10.1109/TCSI.2020.3001654.png)
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摘要
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In order to gain substantial circuit performance improvement in terms of power, speed and area cost, approximate computing is ideally applied in many error-resilient DSP and multimedia applications by relaxing the requirements of exact computation. Fixed-width multipliers are intensively used in those applications, which makes them a good demonstration for approximation through dynamic range reduction. In this paper, a probabilistic prediction based fixed-width Booth multiplier has been proposed. The error compensation function is derived from the probabilistic analysis on the partial products obtained from Booth encoding. By slightly modifying the partial product array with dedicated partitioning, a simple compensation circuit is thus formulated. Compared with the previous works, the proposed design exhibits the best performance-accuracy tradeoff. It achieves at least 27% reduction on the area-energy-delay-error product compared with the other multipliers among various operand lengths. Additionally, the evaluation on 2-Dimensional discrete cosine transform (DCT) circuits indicates that our proposed fixed-width Booth multiplier is applicable for lossy applications with a considerable reduction on hardware expenses and power dissipation while maintaining decent output quality.
Keyword:
Encoding
Probabilistic logic
Hardware
Estimation
Discrete cosine transforms
Finite wordlength effects
Partitioning algorithms
Probabilistic prediction
approximate computing
fixed-width multiplier
Booth encoding
discrete cosine transform (DCT)
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