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A Runtime FPGA Placement and Routing Using Low-Complexity Graph Traversal

delete2015-03-17
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PRE
AI
R
Ricardo Ferreira *
R
Rocha, Luciana
A
André Gustavo dos Santos
J
José Augusto M. Nacif
S
Stephan Wong
L
Luigi Carro
DOI:10.1145/2660775delete
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摘要

摘要

En 中文
Dynamic Partial Reconfiguration (DPaR) enables efficient allocation of logic resources by adding new functionalities or by sharing and/or multiplexing resources over time. Placement and routing (P&R) is one of the most time-consuming steps in the DPaR flow. P&R are two independent NP-complete problems, and, even for medium size circuits, traditional P&R algorithms are not capable of placing and routing hardware modules at runtime. We propose a novel runtime P&R algorithm for Field-Programmable Gate Array (FPGA)-based designs. Our algorithm models the FPGA as an implicit graph with a direct correspondence to the target FPGA. The P&R is performed as a graph mapping problem by exploring the node locality during a depth-first traversal. We perform the P&R using a greedy heuristic that executes in polynomial time. Unlike state-of-the-art algorithms, our approach does not try similar solutions, thus allowing the P&R to execute in milliseconds. Our algorithm is also suitable for P&R in fragmented regions. We generate results for a manufacturer-independent virtual FPGA. Compared with the most popular P&R tool running the same benchmark suite, our algorithm is up to three orders of magnitude faster.
Keyword:
Design
Algorithms
Performance
FPGA
Place and route
Run-time reconfiguration
Graph traversal
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期刊

ACM Transactions on Reconfigurable Technology and Systems 封面图
ACM Transactions on Reconfigurable Technology and Systems
IF:
2.8
论文数:
598
被引数:
810

机构

D
Delft University of Technology
学者数:
2.6W
论文数: 2.5W
被引数: 3.8W
U
Universidade Federal do Rio Grande do Sul
学者数:
2.6W
论文数: 1.7W
被引数: 1.6W
U
universidade federal de vicosa
学者数:
8.9K
论文数: 5.3K
被引数: 5
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