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A single chip motion JPEG codec LSI

delete1997-01-01
delete12
PRE
AI
S
S. Okada *
Y
Yoshio Matsuda
T
Takanori Watanabe
K
Katsuhiko Kondo
DOI:10.1109/30.628651delete
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摘要

摘要

En 中文
We have developed a single chip motion JPEG codec LSI that can compress and decompress VGA-size (640 pixels x 480 lines) JPEG images at the rate of 30 frames per second simply by connecting a single external buffer memory chip. The LSI can control compression ratio control technique to store a fixed number of images when there is limited memory capacity, and it compresses data stored in the frame buffer to enable high-speed signal processing without the use of high-speed image memory. The JPEG codec core is small (40,000 gates) and power consumption is low (220 mW), making it well suited to a wide range of image processing applications in consumer products.

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IEEE Transactions on Consumer Electronics 封面图
IEEE Transactions on Consumer Electronics
IF:
10.9
论文数:
5.3K
被引数:
6.8K

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