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A small data cache for multimedia-oriented embedded systems
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DOI：10.1016/j.sysarc.2007.04.006.png)
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This paper proposes a data cache with small space for low power, but high performance on multimedia applications. The basic architecture is a split-cache consisting of a direct-mapped cache with small block size (DMC) and a fully-associative buffer with large block size (FAB). To overcome the disadvantage caused by small cache areas, two hardware mechanisms are enhanced considering the operational behaviors of multimedia applications: an adaptive multi-block prefetching to initiate various fetch sizes for FAB and an efficient block filtering to remove the data likely to be rarely reused for DMC. The simulations on MediaBench show that the proposed 5kB cache can achieve up to 57% and 50% of power saving while providing almost equal and better performance compared with the 16kB 4-way set associative cache and 17kB stream caches, respectively. (C) 2007 Elsevier B.V. All rights reserved.
Keyword:
data cache
memory hierarchy
multimedia
embedded systems
low power
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