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A Two-Step ADC With Statistical Calibration
DOI:10.1109/TCSI.2020.2978271.png)
摘要
En 中文
This paper describes a prototype two-step ADC with adjustable resolution in 40 nm CMOS technology. It uses a front-end successive-approximation-register ADC and a back-end time-domain ADC. Digital statistical calibration overcomes errors from front-end mismatch as well as inter-stage and back-end nonlinearity by analyzing specific statistical properties. In the 12-bit mode at 20 MS/s, the maximum SNDR is 59 dB before calibration and 68 dB after calibration, using 6.2 fJ per conversion-step, excluding the power dissipation required by the calibration.
Keyword:
Calibration
Histograms
Quantization (signal)
Delays
Prototypes
Probability density function
Capacitors
Two-step ADC
statistical calibration
SAR ADC
time-domain ADC
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期刊
IF:
5.2
论文数:
9.8K
被引数:
2.2W
机构
引用论文
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Synthesis
IF0

