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A Wide Dynamic Range and Low Bit Error Pixel TDC Suitable for Array Application
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DOI：10.1109/TCSII.2019.2894959.png)
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摘要
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This brief presents a cascade pseudo 3-level time-to-digital converter (TDC) based on wideband phase-locked loops (PLLs) for photon time of flight measurement. In each pixel, a 9-bit pseudo random synchronous counter composed of linear feedback shift register is served as a high-level coarse TDC. Its counting clock is directly coming from the synchronous counter served as the middle-level TDC. The low-level fine TDC is based on time-interpolation technology and directly use the low-jitter multi-phase clock signal generated by the PLL to complete the fine quantization of the residue time. In addition, proper timing control and error suppression methods are implemented in the proposed TDC. The circuit is demonstrated in TSMC 0.35- ${\mu }\text{m}$ CMOS process. Under the condition of 10-MHz input reference frequency and 3.3-V supply voltage, the wideband PLL can be locked from 146 to 450 MHz. The resolution of the TDC will change from 856 to 278 ps. At 450 MHz, the measured DNL around $15\boldsymbol {\mu }\text{s}$ is-0.1 to 0.1 LSB and the INL is-0.05 to 0.2 LSB.
Keyword:
Time-to-digital converter
phase-locked loop
wide dynamic range
nonlinearity error
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