Aging Compensation With Dynamic Computation Approximation

doi:10.1109/TCSI.2020.2969462

Aging Compensation With Dynamic Computation Approximation

2020-04-01

10

PRE

AI

DOI：10.1109/TCSI.2020.2969462

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This paper presents a novel design methodology to turn the timing violation caused by aging into computation approximation error without the reliability guardband or increasing the supply voltage. It can be realized by accurately monitoring the critical path delay at run-time. We evaluate the proposal at two levels: RTL component level and system level. The experimental results at the RTL component level show a significant improvement in terms of (normalized) mean squared error caused by timing violation, and those at the system level show that the proposed approach successfully transforms the aging-induced timing violation errors into much less harmful computation approximation errors, and thus it recovers image quality up to perceptually acceptable levels. It reduces the dynamic and static power consumptions by 21.45% and 10.78%, respectively, with 0.8% area overhead compared to the conventional approach.

Keyword:

Aging

Delays

Adders

Monitoring

Integrated circuit reliability

Chip reliability

aging

BTI

design guardband

monitoring circuit

aging monitor

approximation

approximate computing

low power

Aging Compensation With Dynamic Computation Approximation

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