An Analyzable Inter-core Communication Framework for High-Performance Multicore Embedded Systems

doi:10.1016/j.sysarc.2021.102178

An Analyzable Inter-core Communication Framework for High-Performance Multicore Embedded Systems

2021-09-01

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DOI：10.1016/j.sysarc.2021.102178

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Multicore processors provide great average-case performance. However, the use of multicore processors for safety-critical applications can lead to catastrophic consequences because of contention on shared resources. The problem has been well-studied in literature, and solutions such as partitioning of shared resources have been proposed. Strict partitioning of memory resources among cores, however, does not allow intercore communication. This paper proposes a Communication Core Model (CCM) that implements the inter-core communication by bounding the amount of intercore interference in a partitioned multicore system. A system-level perspective of how to realize such CCM along with the implementation details is provided. A formula to derive the WCET of the tasks using CCM is provided. We compare our proposed CCM with Contention-based Communication (CBC), where no private banking is enforced for any core. The analytical approach results using San Diego Vision Benchmark Suite (SD-VBS) for two models indicate that the CCM shows an improvement of up to 65 percent compared to the CBC. Moreover, our experimental results indicate that the measured WCET using SD-VBS is within the bounds calculated using the proposed analysis.

Keywords:

High-performance computing

Communication

Inter-core

Multicore

Heterogeneous systems

Embedded systems

An Analyzable Inter-core Communication Framework for High-Performance Multicore Embedded Systems

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