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An Application Specific Vector Processor for Efficient Massive MIMO Processing
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DOI：10.1109/TCSI.2022.3182483.png)
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This paper presents an implementation for a baseband massive multiple input multiple output (MIMO) application-specific instruction set processor (ASIP). The ASIP is geared with vector processing capabilities in the form of single instruction multiple data (SIMD), and furthermore exploits instruction level parallelism by employing a very large instruction word (VLIW) architecture. Additionally, a systolic array is built into the pipeline which is tuned to speed up matrix calculations. A parallel memory subsystem and stand-alone accelerators are integrated into the ASIP architecture in order to meet the processing requirement. The processor is synthesized in 22 nm FD-SOI technology running at a clock frequency of 800 MHz. The system achieves a maximum detection throughput of 0.75 Gb/s/mm(2) for a 128 x 8 massive MIMO system.
Keyword:
5G
massive MIMO
communications processor
baseband processor
computer architecture
programmable processor
accelerator architecture
vector processor
matrix processor
parallel memory
systolic arrays
VLIW
SIMD
ASIP
期刊
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5.2
论文数:
9.8K
被引数:
2.2W
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