.png){kind=icon}
返回
An Area-Efficient Normal Input/Output Ordered Memory-Based FFT Using an SC Kernel
.png){kind=icon}
PRE
AI
DOI：10.1109/TCSII.2025.3645948.png)
.png){kind=icon}
原文求助.png){kind=icon}
分享.png){kind=icon}
收藏
摘要
En 中文
This brief presents a 1024-point radix-2 memory-based fast Fourier transform (FFT) architecture. This work aims to achieve a normal order at both the input and the output without requiring an additional circuit or memory. The proposed architecture is the first memory-based FFT to utilize a serial commutator (SC) kernel as a processing element (PE). This halves the number of adders and multipliers. Likewise, a novel address generation circuit is presented. It produces the same memory read and write addresses for both memories, as well as conflict-free access. The proposed architecture has been implemented on a Virtex 7 field-programmable gate array (FPGA). The experimental results indicate that it achieves low area, efficient resource utilization, and low power consumption.
Keyword:
FFT
memory-based
normal I/O order
SC
radix-2
期刊
I
IF:
0
论文数:
153
被引数:
0
机构
引用论文
.png){kind=icon}
分享收藏
分享收藏
查看更多内容