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An efficient and cost effective application mapping for network-on-chip using Andean condor algorithm
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DOI：10.1016/j.jnca.2021.103319.png)
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Advancement in very large scale integration (VLSI) technologies and the ever-shrinking size of the transistors have led the semiconductor designers to create a multiprocessor system on chips. Network on chip (NoC) provides an efficient and flexible communication infrastructure to these systems. One of the most prominent research problems in NoC is mapping the real-time application tasks to multiple cores. The aim is to map the cores, which require frequent and high-bandwidth communications close enough to increase the performance and decrease the chip's power consumption. In this research, a nature-inspired Andean condor algorithm (ACA) is applied to the mapping problem of application tasks on multiple cores of NoC. Initially, a clustering-based technique provides the main algorithm a head-start for fast convergence, and then the main ACA is applied to achieve the optimal performance. The simulation results show that the proposed algorithm outperformed state-of-the-art algorithms in terms of various performance metrics, such as communication cost, average packet latency, throughput and energy consumption. The proposed algorithm achieves up to 27.11% improvement in communication cost and provides 78.9% savings in computational overhead.
Keyword:
Andean condor
Application mapping
Communication cost
Computation time
Network on chip
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分享收藏Bandwidth-Constrained Multi-Objective Segmented Brute-Force Algorithm for Efficient Mapping of Embedded Applications on NoC Architecture.png)
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