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An efficient data structure for dynamic two-dimensional reconfiguration
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DOI：10.1016/j.sysarc.2017.02.004.png)
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摘要
En 中文
In the presence of dynamic insertions and deletions into a partially reconfigurable FPGA, fragmentation is unavoidable. This poses the challenge of developing efficient approaches to dynamic defragmentation and reallocation. One key aspect is to develop efficient algorithms and data structures that exploit the two-dimensional geometry of a chip, instead of just one. We propose a new method for this task, based on the fractal structure of a quadtree, which allows dynamic segmentation of the chip area, along with dynamically adjusting the necessary communication infrastructure. We describe a number of algorithmic aspects, and present different solutions. We also provide a number of basic simulations that indicate that the theoretical worst-case bound may be pessimistic. (C) 2017 Elsevier B.V. All rights reserved.
Keyword:
FPGAs
Partial reconfiguration
Two-dimensional reallocation
Defragmentation
Dynamic data structures
Insertions and deletions
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被引数:
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