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An efficient multi-format low-precision floating-point multiplier
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DOI：10.1016/j.suscom.2023.100928.png)
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Low-precision computing has emerged as a promising technology to enhance performance in modern applications like deep neural network training and scientific computing. However, most existing circuits and systems are tailored to a single type of half-precision format, such as FP16 or BFloat16. In light of this limitation, this paper introduces the design of a multi-format floating-point multiplier capable of supporting a wide range of halfprecision formats, including both their signed and unsigned versions. Our design emphasizes high reconfigurability, allowing it to adapt to the required dynamic range and precision. Moreover, experimental results showed that the introduced unsigned versions of the half-precision floating-point formats resulted in improved circuit parameters and energy consumption.
Keyword:
Floating-point multiplier
Low-precision computing
Energy-efficient arithmetic circuits
IEEE FP16
BFloat16
期刊
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IF:
5.7
论文数:
966
被引数:
2.9K
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PROCEEDINGS OF THE IEEE
PROCEEDINGS OF THE IEEEIF25.9
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分享收藏分享收藏Flexible and Scalable FPGA-Oriented Design of Multipliers for Large Binary Polynomials面向FPGA的灵活可扩展大型二进制多项式乘法器设计IEEE ACCESS
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IEEE ACCESSIF3.6
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