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An Efficient Multi-Standard LDPC Decoder Design Using Hardware-Friendly Shuffled Decoding
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DOI：10.1109/TCSI.2012.2215746.png)
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This paper presents an efficient multi-standard low-density parity-check (LDPC) decoder architecture using a shuffled decoding algorithm, where variable nodes are divided into several groups. In order to provide sufficient memory bandwidth without the need for using registers, a FIFO-based check-mode memory, which dominates the decoder area, is used. Since two compensation factors, rather than a single factor, are dynamically used in the offset Min-Sum algorithm, the number of quantization bits, and, hence, the memory size, can be reduced without degradation in error performance. In order to further reduce the memory size, artificial minimum values, which do not need to be stored in memory, are used. We also propose an algorithm that can be used to partition variable nodes such that the hardware cost can be minimized. Using the proposed techniques, amulti-standard decoder that supports the LDPC codes specified in the ITU G.hn, IEEE 802.11n, and IEEE 802.16e standards was designed and implemented using a 90-nm CMOS process. This decoder supports 133 codes, occupies an area of 5.529 mm(2), and achieves an information throughput of 1.956 Gbps.
Keyword:
Channel coding
decoder
G.hn
low-density parity-check codes
LDPC codes
WiMAX
WiFi
期刊
IF:
5.2
论文数:
9.7K
被引数:
2.2W
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分享收藏Reduced complexity iterative decoding of low-density parity check codes based on belief propagation基于置信传播的低密度奇偶校验码迭代译码复杂度降低
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