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An Efficient Neuromorphic Implementation of Temporal Coding-Based On-Chip STDP Learning
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DOI：10.1109/TCSII.2023.3282653.png)
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Fulfilling brain intelligence on the chip has long been a fascinating and challenging endeavor. Numerous neuromorphic computing platforms based on spiking neural networks have simulated the architecture and information processing of the brain, providing new insights to realize artificial intelligence. However, the critical issue still remains how to effectively learn on site. In this brief, we present a neuromorphic processor aimed at performing instant on-chip learning for edge processing purposes. This design adopts a temporal coding based implementation of nearest-neighbor and additive spike-timing-dependent plasticity (STDP) learning method. A pair of spike tracing counters and a reconfigurable look-up table are deployed to perform the STDP weight updating. And a 16-core architecture is also leveraged to enhance learning parallelism and scalability. Integrating up to 2048 neurons and 2M 8-bit synapses, the processor achieves peak performance of 81.92GSOPS and 22.80GSOPS, with energy efficiency of 1.28pJ/SOP and 4.99pJ/SOP in the inference and learning phases, respectively. Validation experiments demonstrate that it achieves recognition accuracies of 93.54%, 59.46%, 72.67% and 79.77% for MNIST, Fashion-MNIST, EMNIST and Chinese-MNIST datasets by on-chip labeling methods, respectively.
Keyword:
Spiking neural network (SNN)
neuromorphic processor
temporal coding
spike-timing-dependent plasticity (STDP)
on-chip learning
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