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An FPGA-Based Approach for Compressing and Accelerating Depthwise Separable Convolution
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DOI：10.1109/LSP.2024.3425286.png)
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Abstract
En 中文
The rapid progress of deep learning has led to an increase in the parameter count and computational requirements of convolutional neural networks (CNN), presenting difficulties in deploying networks on hardware platforms with constrained resources. Although depthwise separable convolution (DSC) is one method used to tackle this issue, it still maintains numerous redundant parameters. Meanwhile, compression learning by in parallel pruning-quantization (CLIP-Q) method represents an efficient approach to network compression. However, it does not have additional optimization for DSC. This study proposes a method named DSC-CLIP-Q, which is derived from the CLIP-Q approach and is designed to specifically address the parameter distribution characteristics of DSC. Furthermore, the research developed a highly energy-efficient and reconfigurable hardware accelerator specifically designed for this approach. Additional storage optimizations tailored to the hardware features of DSC-CLIP-Q is introduced, in conjunction with a reconfigurable processing element (PE) array specifically designed for the convolutional characteristics of DSC. The experimental results indicate that the suggested DSC accelerator attains a high level of throughput and energy efficiency, while also enhancing network accuracy.
Keywords:
Convolution
Optimization
Throughput
Resource management
Quantization (signal)
Parallel processing
Hardware acceleration
CLIP-Q
DSC
FPGA
hardware accelerator
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