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Approximate MAC Unit Using Static Segmentation
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DOI：10.1109/TETC.2023.3315301.png)
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摘要
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In this paper we investigate a novel approximate multiply-and-accumulate (MAC) unit, that computes Y = A x B + C using static segmentation. The proposed architecture uses a unique carry-propagate adder and performs segmentation on the three operands A, B, and C, to reduce hardware cost. The circuit can be configured at design-time by two parameters. The first one controls the segmentation on A and B, while the second one controls the segmentation on C and the adder length. An error compensation technique is also employed, to reduce the approximation error. Error analysis and implementation results in 28nm CMOS for 8-bits multiplier with 20-bits and 24-bits addition are presented. The proposed approximate MACs outperform the state of the art, showing the largest power saving when the mean relative error distance (MRED) is larger than 2 x 10(-3) and 4 x 10(-5) for 20 and 24-bits addition, respectively. For MRED of about 6 x 10(-3) the proposed approximate MAC with 20-bits addition exhibits a power reduction larger than 60% compared to the exact MAC and larger than 27% compared to the state-of-the-art approximate MACs. Application examples to image filtering and template matching show that proposed approximate circuits are good candidates in applications where their error performances are acceptable.
Keyword:
Adders
Multiplexing
Hardware
Computer architecture
Postal services
Image segmentation
Electrical engineering
Approximate methods
arithmetic and logic structures
hardware architecture
low-power design
VLSI
期刊
IF:
5.4
论文数:
1.1K
被引数:
3.4K
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