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Architecture-circuit-technology co-optimization for resistive random access memory-based computation-in-memory chips
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DOI：10.1007/s11432-023-3785-8.png)
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Computation-in-memory (CIM) chips offer an energy-efficient approach to artificial intelligence computing workloads. Resistive random-access memory (RRAM)-based CIM chips have proven to be a promising solution for overcoming the von Neumann bottleneck. In this paper, we review our recent studies on the architecture-circuit-technology co-optimization of scalable CIM chips and related hardware demonstrations. To further minimize data movements between memory and computing units, architecture optimization methods have been introduced. Then, we propose a device-architecture-algorithm co-design simulator to provide guidelines for designing CIM systems. A physics-based compact RRAM model and an array-level analog computing model were embedded in the simulator. In addition, a CIM compiler was proposed to optimize the on-chip dataflow. Finally, research perspectives are proposed for future development.
Keyword:
resistive random-access memory
computation-in-memory
compact model
device-architecture-algorithm co-design
compiler
期刊
IF:
7.6
论文数:
4.9K
被引数:
8.9K
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