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Area-Efficient Parallel Reconfigurable Stream Processor for Symmetric Cryptograph
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DOI：10.1109/ACCESS.2021.3057866.png)
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摘要
En 中文
Represented by application-specific instruction set processors (ASIPs) and array processors, existing cryptographic processors face challenges in application to mobile terminals with sensitive security requirements. Typically, ASIPs have limited computational efficiency and algorithmic adaptability. An array processor requires massive circuits to perform fully expansive computations for ciphers, and such processors are unaffordable for terminals. To overcome these issues, we propose a highly area-efficient parallel reconfigurable symmetric cipher stream processor combining the characteristics of symmetric cryptograph stream-state processing and the advantages of stream architectures. This processor has a hierarchical stream architecture with multi-dimensional parallelism. It decouples cipher computation from data transmission, facilitating parallelism between algorithm operation and data scheduling. Furthermore, the processor fully excavates vertical pipeline parallelism and horizontal block parallelism in its operation processes. Additionally, it takes multi-granular cipher units and reconfigures computation circuits to map different algorithms efficiently. These mechanisms significantly improve its area efficiency and security intensity. The processor's prototype was verified and synthesised in a 65 nm CMOS process. Many typical ciphers were mapped onto the processor. Experimental results demonstrate excellent performance in feedback/no-feedback modes with a small area (1.26 mm(2)). Therefore, its area efficiency is clearly higher than other cipher processors, and it has better prospects for future applications.
Keyword:
Ciphers
Parallel processing
Computer architecture
Scheduling
Registers
Processor scheduling
Pipelines
Stream processor
symmetric cryptograph
area efficiency
parallelism
reconfigurable
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期刊
IF:
3.6
论文数:
9.8W
被引数:
29.4W
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