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Asynchronous DSP for low-power energy-efficient embedded systems
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DOI：10.1016/j.micpro.2011.02.001.png)
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This paper presents the design of an asynchronous DSP that is code compatible with the Motorola DSP56000, with the objective of low power and high energy efficiency to extend the lifespan of the batteries in embedded systems embodying the DSP. It features a unified and low-overhead pipeline flush design, a common-case oriented and efficient single-instruction repeating design, and retimed and single-cycle address generation. The asynchronous DSP is implemented using 130 nm CMOS process and is completely standard-cell based. Pre-layout simulation results demonstrate an equivalent speed of 61.5 MIPS and energy dissipation of 54.5 mu W/MIPS @ 1.2 V running a Radix 2 FFT benchmark program, and a 30.0% energy reduction compared to the clock-gated synchronous counterpart. (C) 2011 Elsevier B.V. All rights reserved.
Keyword:
Digital signal processor
Asynchronous-logic
Low power
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104
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