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Automatic Modulation Recognition: An FPGA Implementation
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DOI：10.1109/LCOMM.2022.3184771.png)
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摘要
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Very recently, convolution neural network (CNN) based deep-learning (DL) models have been used in automatic modulation classification (AMC) systems and achieved superior performance. However, the huge CNN model size and floating-point weights and activation make deployment of such systems very complex with limited hardware resources such as FPGAs. In this work, we have designed CNN-based AMC schemes for the complex-valued temporal radio signal domain and implemented them on an FPGA platform. This work focuses on quantized CNN and low precision mathematics to solve the problem of bigger model size and floating-point weights and activations. However, the low precision weights, activation, and quantized CNN significantly impact the model's accuracy. To overcome this, we proposed an RU-based AMC scheme and used an iterative pruning-based training mechanism to maintain the overall accuracy above a certain threshold while decreasing the model size on hardware. The proposed scheme achieves at least 1.4% higher accuracy and takes only 40% hardware resources than the baseline. The RFSoc implemented model achieves a real-time throughput of 527k classification per second with a latency of 7.5 mu s.
Keyword:
Automatic modulation classification
convolution neural network
iterative pruning
quantization
FPGA
期刊
IF:
4.4
论文数:
1.3W
被引数:
2.2W
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