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C2FPGA-A dependency-timing graph design methodology
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DOI：10.1016/j.jpdc.2012.09.001.png)
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In this paper, we present a design methodology that uses a combined graphical and scheduling technique to map C-based high level language (HLL) based applications to FPGA. Although there are a number of approaches addressing the mapping from HLL to hardware, many of these existing solutions either require a steep learning curve or do not produce an appropriate mapping pattern for the hardware platform. We provide a solution to this problem, by analyzing the data flow and data dependencies in the given code and proposing a scheduling patterns for the given algorithm. We then provide a suitable mapping pattern for the hardware platform. We use the mapping pattern to deliver synthesizable HDL (Verilog) code. We demonstrate our design methodology with results from different real-time case studies that are based on different algorithms. Published by Elsevier Inc.
Keyword:
Data dependency
Compiler
Scheduling
Algorithms
Applications
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4
论文数:
3.8K
被引数:
4.8K
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