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Circuit Reliability Comparison Between Stochastic Computing and Binary Computing
DOI:10.1109/TCSII.2020.2993273.png)
摘要
En 中文
Reliability-enhanced circuit design is increasingly demanded due to severer transistor aging and variations at nanoscale. In this brief, new insights of inherently enhancing reliability are presented, based on the emerging computing paradigm of stochastic computing (SC). A new cross-layer reliability simulation flow supporting statistical static timing analysis (SSTA) is proposed, with a new long-term compact transistor aging model validated by 16/14nm FinFET experimental data. Then, the reliability of SC circuits in practical applications is investigated and compared with that of conventional binary circuits, for the first time. The results indicate that, the performance of SC circuits is intrinsically resistant to aging and variations ascribed to the circuit topology and the probability encoding. It suggests that, SC can provide more relaxed circuit design margins, offering promises to the application of emerging nanodevices in the future.
Keyword:
Aging
Integrated circuit reliability
Integrated circuit modeling
Stochastic processes
Transistors
Computational modeling
Reliability-enhanced design
NBTI
stochastic computing
reliability simulation
FinFET
frequency guardband
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4.9
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8.8K
被引数:
2.5W
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