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Class-based decompressor design for compressed instruction memory in embedded processors
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DOI：10.1109/TC.2003.1244947.png)
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We introduce a new PLA-based decoder architecture for random-access runtime decompression of compressed instruction memory in embedded systems. The compression method employs class-based coding. The symbol codebook used for decompression is fully programmable; thus, good compression may be achieved by adapting the codebook to the symbol frequency statistics of the target binary program. We show that this new class-based decoder architecture can be extended to provide high throughput decompression.
Keyword:
embedded processors
code compression
decompressor architecture
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3.8
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