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Clock-skew-controlled pipeline optimization in superconducting rapid single-flux-quantum circuits
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DOI：10.1587/elex.23.20260050.png)
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Abstract
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This paper presents a clock-skew-controlled pipeline optimization method for superconducting rapid single-flux-quantum (RSFQ) circuits. Without changing the circuit's cell-level topology (netlist connectivity, including the splitter-tree), the pipeline depth along each signal path can be flexibly adjusted by controlling the clock skew between adjacent logic cells. A quantitative relationship between clock skew and latency variation is derived to determine timing configurations at different pipeline depths. A 4-bit adder is designed using cells from the SIMIT Nb03 process library, and a stepwise reduction of its pipeline depth is carried out in simulation to validate the method. At a fixed clock frequency and bias margin, the circuit latency is reduced by 155 ps, while the number of Josephson junctions (JJs) is reduced by about 582.
Keywords:
Rapid single-flux-quantum (RSFQ)
clock skew
pipeline
timing
latency
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